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SN65LVCP114

ACTIVO

Recontrolador lineal cuádruple mux de 14.2 Gbps con acondicionamiento de señal

Detalles del producto

Type Mux Buffer Number of channels 8 Input compatibility AC-coupling Speed (max) (Gbpp) 14.2 Protocols Fibre Channel, General purpose Operating temperature range (°C) -40 to 85
Type Mux Buffer Number of channels 8 Input compatibility AC-coupling Speed (max) (Gbpp) 14.2 Protocols Fibre Channel, General purpose Operating temperature range (°C) -40 to 85
NFBGA (ZJA) 167 144 mm² 12 x 12
  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data
    Rate
  • Linear Receiver Equalization Which Increases
    Margin at System Level of Decision Feedback
    Equalizer
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port
    to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm
    Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB
    Transmission Lines
  • Small Package Size Provides Board Real Estate
    Saving
  • Adjustable Output Swing Provides Flexible EMI
    and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability
    to Transparency for Link Training
  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data
    Rate
  • Linear Receiver Equalization Which Increases
    Margin at System Level of Decision Feedback
    Equalizer
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port
    to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm
    Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB
    Transmission Lines
  • Small Package Size Provides Board Real Estate
    Saving
  • Adjustable Output Swing Provides Flexible EMI
    and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability
    to Transparency for Link Training

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65LVCP114 14.2-Gbps Quad 1:2-2:1 Mux, Linear-Redriver With Signal Conditioning datasheet (Rev. A) PDF | HTML 01 abr 2016
Application note Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) 31 ene 2023
Application note The Benefits of Using Linear Equalization in Backplane and Cable Applications 31 ene 2013
User guide SN65LVCP114 EVM Graphical User Interface Guide 18 ene 2012
EVM User's guide SN65LVCP114 EVM User's Guide 18 ene 2012
Application note SN65LVCP114 Guidelines for Skew Compensation 17 ene 2012

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

GUI para el módulo de evaluación (EVM)

SLLC426 SN65LVCP114 EVM GUI

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Retardadores, redrivers y mux-búferes Ethernet
SN65LVCP114 Recontrolador lineal cuádruple mux de 14.2 Gbps con acondicionamiento de señal
Modelo de simulación

SN65LVCP114 Sparameter Model

SLLM168.ZIP (1157 KB) - S-Parameter Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
NFBGA (ZJA) 167 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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Soporte y capacitación

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