7 Important Takeaways

This application note provides a detailed explanation of different ADC timing components, how multiplexed delta-sigma ADCs sample and process data, and how to use the information in the ADC data sheet to select a device that meets system cycle-time requirements. The following list summarizes the key points presented in this document:

• Delta-sigma modulator data takes some time to propagate through the digital filter, resulting in conversion latency
• Sinc filter conversion latency is approximately equal to a number of conversion periods equivalent to the sinc filter order. For example, a sinc³ filter typically has three conversion period latency
• ADCs do not have a way to identify significant changes in the input signal, such as when a step input occurs. Ensure that the input signal is settled before starting the conversion process
• Under certain conditions, some ADCs can hide unsettled data from the user
• First conversion data is subject to conversion latency proportional to the sinc filter order, while second and subsequent conversion data can be approximated as 1 / ODR in most cases
• Single-shot mode requires the digital filter to reset after each conversion result, providing all data at a rate equivalent to first conversion latency. Continuous-conversion mode typically provides second and subsequent data at a rate of 1 / ODR
• Some ADCs include a programmable delay to account for external analog settling before the conversion process begins. This delay occurs once when conversions are triggered and scales with the clock frequency
• Each ADC includes an overhead time to process data before the conversion result is available. This time affects the first conversion latency only, cannot be changed by the user, and scales with the clock frequency
• The ODR, the programmable delay, and the ADC overhead time scale with the clock frequency. This enables the user to increase or decrease the conversion latency compared to the nominal value without changing any other system settings
• Chopping swaps the polarity of the input signal and averages two conversions to produce a settled conversion result. As such, the digital filter must reset after each conversion, requiring two first conversion latency periods to generate a single, settled output
• External signal conditioning circuitry has some finite bandwidth that can cause analog inputs to be unsettled when the ADC conversion process begins. The programmable delay can be used to account for any analog settling delay, though this increases the total conversion latency