6 Analog Settling

While the previous sections discussed how certain features and modes integrated into the ADC affect conversion latency and cycle time, one common external factor that affects timing is analog settling. External signal conditioning circuitry such as amplifiers or filters has a finite bandwidth. Additionally, some ADCs have internal analog filters that have a well-defined settling time. As a result, an analog signal takes some amount of time to propagate through these components before it is sampled by the ADC. This analog signal could be an input from a sensor, or it could be a biasing signal such as a current source or an excitation voltage. In any case, it is necessary to account for analog settling time in the overall conversion latency. Otherwise, the ADC will sample an unsettled signal that will show up as an error in the ADC conversion result. This noise can be erroneously attributed to crosstalk or other errors even though it is actually the result of sampling an unsettled signal.

As an example, a simple low-pass RC filter used for anti-aliasing has some time constant, τ, that might prohibit the input signal from settling before the ADC starts converting. Figure 6-1 shows the differential filter circuit commonly used at the input to a delta-sigma ADC on the left and its corresponding settling time in the plot on the right.

Figure 6-1 Step Response and Settling Time for an RC Filter

As shown, Figure 6-1 assumes there is initially 0 V across the capacitor in the example system. Then, at τ = 0, the 5-V analog step input is applied to the capacitor, which is the black plot shown in Figure 6-1. The capacitor cannot respond to this voltage immediately, and instead takes some time to ramp to the applied value, as per the response shown in red. While this plot appears to show that the output settles after approximately 5 ∙ τ, many high-resolution delta-sigma ADCs can distinguish much finer analog signals than the RC output amplitude at 5 ∙ τ. In fact, it takes more than 17 ∙ τ for the RC output signal to reach ½ of a least significant bit (LSB) for a 24-bit ADC. Waiting 17 ∙ τ might be unnecessary for some applications, though even 20-bit resolution takes almost 15 ∙ τ to settle to ½ of an LSB. The relationship between ADC resolution and the number of time constants to settle to ½ LSB (τ_LSB) can be calculated using Equation 14.

where

• N is the ADC resolution

Table 6-1 uses Equation 14 to calculate the number of time constants required for the analog filter to settle to ½ LSB for several common ADC resolution values.

One important caveat to the information in Table 6-1 is that the actual RC output settling time depends on the magnitude of the ADC LSB as well as the magnitude of the change in the input voltage. If the ADC reference voltage is small or the gain is large, it is often impractical to settle to ½ LSB because the LSB size is well below the inherent noise of the ADC. Instead, target the magnitude of the system noise at the desired data rate and gain settings. Additionally, if the applied voltage changes from 4.99 V to 5 V for example, it will not be necessary to wait the time specified in Table 6-1 to reach the corresponding ADC resolution. Therefore, consider analog settling time when the input signal changes very quickly, when the value of τ is large, or when the magnitude of the input signal changes significantly after each conversion.

As mentioned previously, some ADCs include a programmable delay that occurs immediately before the conversion process to account for external factors such as a multiplexer change or analog settling. For example, assume that a design calls for 20-bit resolution and includes an RC anti-aliasing filter where τ = 15 µs. Table 6-1 reveals that 14.56 ∙ τ seconds are required to settle to 20-bit resolution, which is a total analog settling time of 14.56 ∙ 15 µs = 218.4 µs. The ADS124S08 programmable delay options in Table 5-3 – where t_MOD = 3.9 µs when f_CLK = 4.096 MHz – determine that the system requires at least 218.4 / 3.9 = 55.9 ∙ t_MOD periods to accommodate the analog settling time. Therefore, set DELAY[2:0] = 010b to wait 64 t_MOD periods and allow enough time for the RC output to fully settle before the ADC starts the conversion process.

Ultimately, it is important to consider how external signal conditioning circuitry can impact analog settling time because this directly adds to the overall ADC conversion latency.