Many delta-sigma ADCs offer chopping functionality to help reduce errors and improve accuracy. Chopping is a sampling technique that averages two conversions together: one with normal polarity, and another with reverse polarity, which generates a final conversion result that is virtually free from offset or mismatch errors. Some examples of different chopping techniques include:

• Input (global) chop – remove offsets internal to the ADC, similar to constant offset calibration
• Bridge chop (AC excitation) – typically used with Wheatstone bridge circuits to remove offsets from the signal conditioning circuitry external to the ADC
• IDAC chop (rotation) – used with two-IDAC, 3-wire RTD systems to eliminate the effects of IDAC mismatch

Chopping impacts conversion latency because multiple conversions are required to determine a single, chopped conversion result. Moreover, the digital filter resets after each conversion even though the same channel is being sampled because the input polarity is swapped. This behavior is described and quantified in the ADC data sheet. For example, Figure 5-6 shows how the ADS124S08 processes data for both the low-latency and sinc³ filters when global chop is enabled.

Figure 5-6 Global Chop Conversion Mode Sequences Using the ADS124S08 Low-Latency and Sinc³ Filters

After initiating a conversion, the low-latency and sinc³ filters in Figure 5-6 both take two complete first conversion latency periods – each including programmable delay and ADC overhead time – before the first conversion result is ready. As noted previously, this is because the input signal polarity is swapped after each conversion, requiring the digital filter to reset each time. As an example, it takes 30.254 ms to get a settled, first conversion result from the ADS124S08 sinc³ filter at an ODR = 100 SPS as per Table 5-1. When global chop mode is enabled, this time doubles to 2 ∙ 30.254 ms = 60.508 ms, resulting in an effective data rate of 16.5 SPS for first conversion data.

Second and subsequent conversions follow a similar process as outlined in Section 5.2. If the ADC is in single-shot mode and the user triggers a second conversion on the same channel, the entire process restarts. This requires two new conversions to be averaged together, and therefore two additional first conversion latency periods to generate one, settled conversion result. If the ADC is in continuous-conversion mode, a second or subsequent conversion averages the previous conversion with the current conversion to generate the next settled conversion result. This behavior only requires one additional first conversion latency period. Second and subsequent conversion behavior in continuous-conversion mode is also shown in Figure 5-6. Continuing the previous example where the first conversion result took 60.508 ms at ODR = 100 SPS with global chop enabled, generating a second or subsequent conversion result in continuous-conversion mode takes 30.254 ms.

Not all ADCs offer chopping functionality, nor is all chopping behavior the same. Refer to the specific ADC data sheet to determine how to calculate conversion latency when chopping functionality is enabled.