The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
| Documentación principal | Tipo | Título | Opciones de formato | Fecha |
|---|---|---|---|---|
| * | Data sheet | ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device datasheet (Rev. A) | PDF | HTML | 29 jun 2015 |
| Design guide | ADS58J63_A_DESIGN_PACKAGE | 17 jun 2015 |
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| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
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Analog Engineer's Calc Installer
General calculator tool for analog design support.
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