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Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADS4145

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14-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS4145

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 136 Architecture Pipeline SNR (dB) 73.9 ENOB (bit) 11.5 SFDR (dB) 87 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 136 Architecture Pipeline SNR (dB) 73.9 ENOB (bit) 11.5 SFDR (dB) 87 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Ultra-Low Power With 1.8-V Single Supply:
    • 103-mW Total Power at 65 MSPS
    • 153-mW Total Power at 125 MSPS
  • High Dynamic Performance:
    • SNR: 72.2 dBFS at 170 MHz
    • SFDR: 81 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Idle Channel SNR 74.8 dBFS (ADS414x)
  • Output Interface:
    • Double Data Rate (DDR) LVDS With Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200 mVPP
  • Ultra-Low Power With 1.8-V Single Supply:
    • 103-mW Total Power at 65 MSPS
    • 153-mW Total Power at 125 MSPS
  • High Dynamic Performance:
    • SNR: 72.2 dBFS at 170 MHz
    • SFDR: 81 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Idle Channel SNR 74.8 dBFS (ADS414x)
  • Output Interface:
    • Double Data Rate (DDR) LVDS With Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200 mVPP

The ADS412x and ADS414x devices are lower-sampling speed variants in the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x and ADS414x devices have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x and ADS414x devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

The ADS412x and ADS414x devices are lower-sampling speed variants in the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x and ADS414x devices have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x and ADS414x devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).
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Technical documentation

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Type Title Date
* Data sheet ADS41xx 14-, 12-Bit, 65-, 125-MSPS, Ultra-Low-Power ADC datasheet (Rev. C) PDF | HTML 08 Jun 2017
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
User guide ADS41xx/58B18EVM User's Guide (Rev. D) PDF | HTML 15 Mar 2022
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
Application note High-Speed, Analog-to-Digital Converter Basics 11 Jan 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

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