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High-speed ADCs (≥10 MSPS)

ADS5292

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Eight-Channel, 12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS5292

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 80 Resolution (Bits) 12, 14 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 376 Architecture Pipeline SNR (dB) 72 ENOB (bit) 11.3 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 80 Resolution (Bits) 12, 14 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 376 Architecture Pipeline SNR (dB) 72 ENOB (bit) 11.3 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
HTQFP (PFP) 80 196 mm² 14 x 14
  • Maximum Sample Rate: 80 MSPS/12-Bit
  • High Signal-to-Noise Ratio
    • 70-dBFS SNR at 5 MHz/80 MSPS
    • 71.5-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter = 2
    • 85-dBc SFDR at 5 MHz/80 MSPS
  • Low Power Consumption
    • 48 mW/CH at 50 MSPS
    • 54 mW/CH at 65 MSPS
    • 66 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
  • Digital Processing Block
    • Programmable FIR Decimation Filter and Oversampling to Minimize
      Harmonic Interference
    • Programmable IIR High Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-=Channel Averaging
  • Flexible Serialized LVDS Outputs:
    • One or Two wires of LVDS Output Lines per Channel Depending on ADC
      Sampling Rate
    • Programmable Mapping Between ADC Input Channels and LVDS Output
      Pins-Eases Board Design
    • Variety of Test Patterns to Verify Data Capture by
      FPGA/Receiver
  • Internal and External References
  • 1.8V Operation for Low Power Consumption
  • Low-Frequency Noise Suppression
  • Recovery From 6-dB Overload within 1 Clock Cycle
  • Package: 12-mm × 12-mm 80-Pin QFP
  • Maximum Sample Rate: 80 MSPS/12-Bit
  • High Signal-to-Noise Ratio
    • 70-dBFS SNR at 5 MHz/80 MSPS
    • 71.5-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter = 2
    • 85-dBc SFDR at 5 MHz/80 MSPS
  • Low Power Consumption
    • 48 mW/CH at 50 MSPS
    • 54 mW/CH at 65 MSPS
    • 66 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
  • Digital Processing Block
    • Programmable FIR Decimation Filter and Oversampling to Minimize
      Harmonic Interference
    • Programmable IIR High Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-=Channel Averaging
  • Flexible Serialized LVDS Outputs:
    • One or Two wires of LVDS Output Lines per Channel Depending on ADC
      Sampling Rate
    • Programmable Mapping Between ADC Input Channels and LVDS Output
      Pins-Eases Board Design
    • Variety of Test Patterns to Verify Data Capture by
      FPGA/Receiver
  • Internal and External References
  • 1.8V Operation for Low Power Consumption
  • Low-Frequency Noise Suppression
  • Recovery From 6-dB Overload within 1 Clock Cycle
  • Package: 12-mm × 12-mm 80-Pin QFP

Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.

The ADS5292 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. A unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.

The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.

The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294.

Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.

The ADS5292 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. A unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.

The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.

The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294.

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Technical documentation

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Type Title Date
* Data sheet Octal Channel 12-Bit, 80 MSPS and Low-Power ADC datasheet (Rev. B) 25 Jul 2012
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
EVM User's guide ADS5292 EVM (Rev. A) 05 Mar 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note Understanding Serial LVDS Capture in High-Speed ADCs 10 Jul 2013

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