Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1600 Architecture Pipeline SNR (dB) 60.8 ENOB (bit) 9.8 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1600 Architecture Pipeline SNR (dB) 60.8 ENOB (bit) 9.8 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer No
NFBGA (ZAY) 196 144 mm² 12 x 12
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3 dB): >1.2 GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 910 mW/ch
  • Performance at fin = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 77 dBc
  • Performance at fin = 700 MHz IF
    • SNR: 59.4 dBFS
    • SFDR: 70 dBc
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3 dB): >1.2 GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 910 mW/ch
  • Performance at fin = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 77 dBc
  • Performance at fin = 700 MHz IF
    • SNR: 59.4 dBFS
    • SFDR: 70 dBc

The ADS5404 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS5404 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

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* Data sheet Dual Channel 12-Bit 500Msps Analog to Digital Converter, ADS5404 datasheet (Rev. B) 08 Jan 2014
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide ADS540x and ADS54T0x Evaluation Module 28 Jun 2012
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011

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