ADC3910S125
- Sampling rate up to 125MSPS
- Latency: 1 clock cycle
- Low power (2 channel):
- 92mW at 125MSPS
- 59mW at 25MSPS
- 4mW in PD mode
- Small footprint: 32-VQFN (4mm x 4mm)
- Single or dual channel ADC
- Dual digital comparators
- Reference: internal or external
- No missing codes, ±1 LSB INL
- Buffered, differential or single ended inputs
- Input bandwidth: 150MHz (3-dB)
- Single 1.8V supply
- Optional 3.3VIO capability
- Industrial temperature range: -40 to 105°C
- On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16
- Parallel (SDR, DDR) and serial CMOS interface
- Spectral performance (fIN = 5MHz):
- SNR: 61dBFS
- SFDR: 65dBc
The ADC3910Dx and ADC3910Sx are a family ultra-low power 10-bit 125MSPS high-speed single and dual channel analog-to-digital converters. High-speed control loops benefit from the short latency of only 1 clock cycle. The ADC consumes only 92mW at 125Msps with a power consumption that scales with lower sampling rates.
The device uses DDR, HDDR, SDR or serial CMOS interface to output the data from +1.8V to +3.3V to accommodate various receiver requirements. The device implements analog monitoring function by event triggered interrupts per channel using a digital comparator with programmable high and low thresholds, hysteresis, and event counter. The device is a pin-to-pin compatible family of ADCs with 8 and 10-bit resolution and different speed grades. The device is available in a 32-pin VQFN package, and supports industrial temperature range from -40 to +105°C.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | ADC3910Dx and ADC3910Sx 10-bit, 25 to 125MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers datasheet (Rev. A) | PDF | HTML | 2024/05/15 |
설계 및 개발
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ADC3910D125EVM — ADC3910D125 평가 모듈
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패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
VQFN (RSM) | 32 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치